1. Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to the implementation branch target buffers within processors.
2. Description of the Related Art
To improve performance, processors may attempt to exploit instruction-level parallelism (ILP) by simultaneously executing independent instructions. For example, a processor may execute instructions or portions of instructions before it is know if the instructions actually need to be executed. This technique is commonly referred to as “speculative execution.”
To employ speculative execution within a processor, it is necessary to predict or “guess” how conditional branches (if-then-else structures within a computer program) are going to evaluate. Once a “branch prediction” has been made for a given conditional branch, a processor may be able to fetch and execute the instructions along the predict path, thereby allowing the execution pipeline with the processor to remain full and not stall. In the case when the branch prediction proves to be inaccurate, however, a processor's pipeline may stall while the actual instructions are fetched from memory.
Branch prediction may take several forms. For example, direction prediction may predict if a branch is taken, while target prediction may predict the target address of branch that is taken. Specialized hardware, such as, e.g., branch target buffers, may be employed for making predictions. A branch target buffer may be designed in accordance with one of various designs styles, and may include, multiple prediction entries organized in a table. During the execution of a computer program, entries within a branch target buffer may be updated to improve prediction accuracy.